NGS tunes tiny transistors for future chips
Friday 04 December 2009
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The BBC has reported that the NGS has provided about 20 years worth of processing time to simulate transistors smaller than 30 nanometres to enable future generations of chips to be designed with more processing power.
"What we do in these simulations is try to predict the behaviour of these devices in the presence of atomic scale effects," said Professor Asen Asenov, head of the device modelling group at the University of Glasgow, which is leading the NanoCMOS simulation project.
"What's happening at such dimensions is that the atomic structure of the transistor cannot be precisely controlled," he said. "In order to make them work we have to put in impurities to define different regions."
To increase their processing power silicon chips cannot just be built bigger because of the heat generated when they are used, so they have to be packed more densely. The current generation of chips use transistors with features around 32 nanometres in size, but many manufacturers will move to 22 nanometres soon. The simulated size of 30 nanometres would be a further step reduction in size providing an increase in packing density and consequent increase in processing power.
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